This Phase Locked Loop is modeled after the CMOS 4046 chip, but without any frequency limitations. With specifications of bandwidth and damping, it will model any realizable second order loop with any of three phase comparators and passive or active loop filters.
Dialog Choices
Bandwidth and Damping: These two parameters define the response of the loop in terms of servo theory (see Floyd M. Gardner, Phaselock Techniques, John Wiley & sons, NY, 1979).
Frequency Multiplier: This integer is used to divide the VCO output before it is sent to the phase comparator. The overall effect of the PLL is to multiply the input frequency by this value. If it is greater than 1, remember to multiply the VCO Output Frequency Limits (below) by this value.
VCO Output Frequency Limits: These are the frequency limits of the VCO. Remember to multiply these values by the Frequency Multiplier (above).
Loop Filter: Choose Passive RC or Active Integrator.
Phase Comparator: See the specifications for the CMOS 4046 PLL chip for explanations of these phase comparators.
Connectors
In: This signal input has a threshold of 0.5 volts. Any input below 0.5 volts is a digital low. Any input greater than 0.5 volts is a digital high.
Freq Out: This is the square wave PLL VCO output.
Demod Out: This is the actual voltage control input to the VCO, so it has high frequency phase comparator components that may need to be filtered out with a low pass filter before using it as a demodulator output.
PP (Phase Pulses): This output is used only when the Frequency Tri-State phase comparator is selected. It goes high for the absolute time between the positive edge of the input pulse and the positive edge of the divided VCO output. It can be used to determine a locked condition when it becomes very narrow.
